The present invention generally relates to semiconductor memory device technology, and more particularly relates to a semiconductor memory device performing reading and writing at regular intervals in synchronism with clock pulses externally supplied.
In recent years, semiconductor memory devices of various types, like synchronous DRAM's, operating at a high speed in synchronism with external clock pulses have been applied to numerous appliances.
In such a clocked semiconductor memory device, a timing signal is produced as a trigger for activating respective circuit components within the device responsive to an external clock pulse. As for a DRAM, a column-select-gate-activating signal is used as one of such timing signals. The column-select-gate-activating signal is used for controlling the ON/OFF states of a specific column-select gate provided between a pair of bit lines, associated with each of a great number of columns in an array of memory cells, and a pair of data lines. After a particular column-select gate has been specified in response to a given column address, the column-select gate is kept ON to connect a pair of bit lines, associated with the column-select gate, to the pair of data lines so long as the column-select-gate-activating signal is asserted.
During reading, data, which has been read out from a selected memory cell onto the associated pair of bit lines, is amplified by a sense amplifier and then transferred to the pair of data lines via the associated column-select gate that has been turned ON. The data, which has arrived at the pair of data lines, is further amplified by a read amplifier and then output to the outside of the device through a data output circuit.
On the other hand, during writing, data, which has been input from the outside of the device, is supplied to a write amplifier via a data input circuit. In response to the data supplied, the write amplifier drives the pair of data lines and then transfers the data to the associated pair of bit lines via the associated column-select gate that has been turned ON.
FIG. 4 is a timing diagram illustrating an exemplary operation of a conventional semiconductor memory device. In FIG. 4, CLK denotes an external clock signal; /CS, /RAS, /CAS and /WE respective control signals; IRW a column-select-gate-activating signal; and Y a column-select signal for controlling a column-select gate. In the example illustrated in FIG. 4, reading is performed first, and in response to the input of a write command in synchronism with the third leading edge of the external clock signal CLK, the mode of operation is switched from reading into writing. The write command is input after the control signals /CS, /CAS and /WE have been asserted as logically low and while the control signal /RAS is negated as logically high. The column-select signal Y is asserted as logically high while the column-select-gate-activating signal IRW is high. When the column-select signal Y is asserted, the associated column-select gate turns ON. As a result, the associated pair of bit lines are connected to the pair of data lines.
The conventional semiconductor memory device, however, causes the following problems if the device is operated at a higher speed with the frequency of the external clock signal increased.
In writing specified data into a selected memory cell, the write amplifier should drive not only the pair of data lines but also the associated pair of bit lines via the column-select gate to invert the data latched in the sense amplifier. Accordingly, while allowing the potentials on the pair of data lines to swing greatly, the column-select gate should be kept ON for a time long enough to connect the associated pairs of bit lines to the pair of data lines. That is to say, in performing writing, a time required for establishing a connection between the pairs of data lines and bit lines should be sufficiently long.
In contrast, during reading, since the potentials on the pair of data lines usually swing more slowly, these potentials should be equalized with each other to a large degree before the data is read out. Otherwise, it would take an adversely long time to completely erase the previous data remaining on the pair of data lines, thus delaying reading accordingly. In other words, during reading, a time required for equalizing the potentials on the pair of data lines with each other should also be long enough.
In the conventional semiconductor memory device, however, the column-select-gate-activating signal IRW is cyclically asserted/negated at the same regular intervals no matter whether the mode of operation is reading or writing. Accordingly, the interval, in which a column-select gate is ON, i.e., the time for connecting a pair of data lines to an associated pair of bit lines, is the same irrespective of the mode of operation.
Such a conventional semiconductor memory device cannot operate stably enough at a high speed if the frequency of an external clock signal is increased. In other words, if a pair of data lines are to be connected to an associated pair of bit lines within a sufficiently long time during writing, then it is difficult to afford an abundant time for equalizing the potentials on the pair of data lines during reading. Nevertheless, if a rather long time is allotted for equalizing the potentials on the pair of data lines during reading by shortening the time for connecting the pairs of data lines and bit lines, then it is hard to allow plenty of time for connecting these lines during writing.